Japanese Laid-open Patent Publication No. 2011-198143 (referred to as “Patent Document 1”, hereinafter) discloses a design support program that carries out wiring verification for a tentative wiring area, and if there is an unwired net determined as a result of the wiring verification, the tentative wiring area is enlarged to set a new tentative wiring area.
Japanese Laid-open Patent Publication No. 2010-211753 (referred to as “Patent Document 2”, hereinafter) discloses a support method that defines for at least each pin of an integrated circuit package, between horizontal pins, between vertical pins, and between diagonal pins, wiring bottleneck places to give a wiring capacity to each of the bottleneck places. The method disclosed in Patent Document 2 generates two nodes, which are an entrance node and an exit node, for each bottleneck place, and generates directed branches from the entrance node to the exit node in the respective bottleneck places, etc.
However, according to the configuration disclosed in Patent Document 1, there is a problem that a designer cannot obtain quantitative information about how a change in a part arrangement design or a wiring design on a substrate affects wirings around the changed portion if the change is performed. This also holds true for the configuration disclosed in Patent Document 2.